The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a 1-hot vector tag plus valid bit protection scheme and/or a 2-hot vector tag protection scheme in high speed memories, such as caches.
Modern high-performance processors, for example, Intel(copyright) Architecture 32-bit (IA-32) processors, include on-chip memory buffers, called caches, to speed up memory accesses. IA-32 processors are manufactured by Intel Corporation of Santa Clara, Calif. These caches generally consist of a tag array and a data array. The data array generally stores the data that is needed during the execution of the program. The tag array generally stores either a physical address or a virtual address of the data as tags. For reliability reasons, these stored tags are often protected for error detection by associating a separate parity bit with each tag. In even higher performance processors, for example, Intel(copyright) Architecture 64-bit (IA-64) processors, each tag is generally stored as a 1-hot vector in a 1-hot cache, which is derived during a Translation Look-aside Buffer (TLB) lookup for an address translation. IA-64 processors are manufactured by Intel Corporation of Santa Clara, Calif. A xe2x80x9c1-hot vectorxe2x80x9d is an n-bit, binary address in which a single bit is set to specify a matching address translation entry in the TLB. The advantage of using a 1-hot vector as a tag is that it improves the operating frequency of a cache. Unfortunately, the protection of these 1-hot vectors presents a great challenge since the conventional parity bit protection scheme used to protect the standard tag in the conventional cache does not work well for the 1-hot vectors. For example, when an entry in the TLB is replaced, all of the tags with the corresponding 1-hot vectors in the 1-hot cache must be invalidated. This invalidation can be performed using a blind invalidate operation, in which all 1-hot vectors in the cache with the xe2x80x9c1xe2x80x9d bit matching the selected TLB entry will be invalidated. However, since the blind invalidate operation only overwrites the 1-hot vector and not the associated parity bit, the associated parity bit is no longer valid for the new value in the 1-hot vector. In addition, in the 1-hot cache, since all of the cleared bits are now zero, if any of the bits are changed by a soft error to a 1, then, the cleared entry becomes a 1-hot vector, which is indistinguishable from a real, valid 1-hot vector that also may be stored in the 1-hot cache. A xe2x80x9csoftxe2x80x9d error is an error that occurs when a bit value that is set to a particular value in the processor is changed to an opposite value by, for example, an alpha particle bombardment and/or gamma-ray irradiation of the bit.
A straight forward protection scheme for the 1-hot tag cache that does work for the 1-hot vectors involves having a second tag array to maintain a duplicate copy of the 1-hot vectors in the tag array. However, although this duplicate tag array scheme works, it requires a larger chip area and a high timing impact to implement.